AMD has begun the production ramp of its sixth-generation EPYC processor, codenamed Venice, on Taiwan Semiconductor Manufacturing Company’s 2-nanometre process technology, setting up a new phase in the contest to supply processors for cloud computing, enterprise infrastructure and artificial intelligence systems.The Santa Clara-based chip designer said Venice is being ramped in Taiwan and is planned for later production at TSMC’s Arizona fabrication facility. The company described the processor as the first high-performance computing product to enter production ramp on TSMC’s advanced 2nm technology, a milestone that places AMD among the earliest major customers using the foundry’s newest manufacturing node for server-class silicon.
Venice is expected to form the next major step in AMD’s EPYC roadmap after the Turin generation, strengthening the company’s position in a server market being reshaped by AI inference, autonomous AI agents and larger memory-hungry workloads. AMD has not released full commercial specifications, pricing or launch volumes, but the processor is tied to the Zen 6 architecture and is aimed at data centres where power efficiency, core density and memory bandwidth are becoming decisive procurement factors.
AMD chair and chief executive Lisa Su said the ramp marked “an important step forward in accelerating the next generation of AI infrastructure”, adding that customers needed platforms that could move faster from innovation to production as AI and agentic workloads scale. The comment underlines AMD’s effort to position EPYC not only as a conventional server CPU line, but as a core component of AI infrastructure alongside accelerators, networking and advanced packaging.
TSMC’s 2nm platform is a critical part of that strategy. The N2 process introduces nanosheet transistor technology, replacing the FinFET structures that defined earlier leading-edge nodes. The shift is designed to improve performance and reduce power consumption, giving chip designers more room to build processors for workloads that demand heavy parallel computation while keeping energy costs under control.
For AMD, the move comes as demand for CPUs has tightened across the global supply chain. AI spending has been led by graphics processors, but central processors remain essential for data preparation, orchestration, inference serving, storage, networking and general cloud workloads. As more enterprises deploy AI systems that act across software environments, CPU demand has broadened beyond traditional web services and database applications.
AMD’s data centre business has already become its main growth engine. First-quarter 2026 data centre revenue reached $5.8 billion, up 57 per cent from a year earlier, driven by EPYC processors and Instinct GPU shipments. Total quarterly revenue stood at $10.25 billion, up 38 per cent year on year, while the company projected second-quarter revenue of about $11.2 billion, reflecting continued strength in server and AI demand.
Venice also deepens AMD’s reliance on Taiwan’s semiconductor ecosystem. Beyond wafer manufacturing, advanced AI chips require complex packaging, substrates, printed circuit boards and system assembly. AMD has outlined more than $10 billion in Taiwan-linked AI sector investments and is working with partners including ASE, SPIL, PTI, Wiwynn, Wistron, Inventec, Unimicron, Nan Ya PCB and Kinsus to secure capacity for the rest of the decade.
Competition remains intense. Intel is attempting to rebuild its data centre position through new server platforms and its foundry roadmap, while Nvidia is expanding beyond GPUs into CPUs for AI systems. Cloud providers are also designing custom processors to reduce cost and improve workload control. AMD’s advantage rests on its chiplet architecture, proven EPYC adoption among major cloud platforms and access to TSMC’s most advanced manufacturing capacity.
The Venice ramp also signals the next stage of AMD and TSMC’s long collaboration. AMD’s server gains over the past several years have been built on a combination of chiplet design, TSMC manufacturing and aggressive platform execution. The use of 2nm technology extends that model into a more capital-intensive phase, where early access to advanced nodes may determine which suppliers can meet performance-per-watt targets for AI-era infrastructure.
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